Title :
A 10 Gb/s CMOS clock and data recovery circuit with frequency detection
Author :
Savoj, J. ; Razavi, B.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
A 10 Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. In 0.18 /spl mu/m CMOS technology, the circuit exhibits 1.43 GHz capture range and 0.8 ps rms jitter with length 2/sup 23/ PRBS. The power dissipation is 91 mW from a 1.8 V supply.
Keywords :
CMOS digital integrated circuits; detector circuits; jitter; phase locked loops; synchronisation; 0.18 micron; 1.8 V; 10 Gbit/s; 91 mW; CMOS; automatic data retiming; capture range; clock and data recovery circuit; frequency detection; multiphase LC oscillator; phase-locked loop; power dissipation; rms jitter; CMOS technology; Circuits; Clocks; Jitter; Phase detection; Phase frequency detector; Resonance; Ring oscillators; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912554
