DocumentCode
2981688
Title
A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply
Author
Yong-In Park ; Karthikeyan, S. ; Tsay, F. ; Bartolome, E.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
130
Lastpage
131
Abstract
A 100 MHz ADC for low-power applications uses a 0.18 μm digital CMOS process. The design achieves 9.4 ENOB for a 50 MHz input at full sampling rate, and consumes a total of 180 mW with 2.5 mm/sup 2/ core in a single 1.8 V power supply.
Keywords
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; low-power electronics; pipeline processing; 1.8 V; 10 bit; A/D convertor; CMOS pipelined ADC; digital CMOS process; low-power applications; CMOS process; Capacitors; Circuits; Clocks; Dynamic range; Energy consumption; Pipelines; Power supplies; Resistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912573
Filename
912573
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