Title :
A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist
Author :
Kelly, D. ; Yang, W. ; Mehr, I. ; Sayuk, M. ; Singer, L.
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
Abstract :
A 14 b multi-bit ADC with a switched-capacitor pipeline architecture achieves 0.6 LSB DNL and 2 LSB INL without calibration. Typical SNR is 73 dB, while SFDR is >85 dB for input frequency up to Nyquist. The 7.8 mm/sup 2/ ADC in 0.35 μm double-poly triple-metal process operates with a 2.7 V to 3.6 V power supply, and consumes 340 mW at 3 V.
Keywords :
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; pipeline processing; switched capacitor networks; 0.35 micron; 14 bit; 2.7 to 3.6 V; 3 V; 340 mW; 73 dB; CMOS ADC; SC pipeline architecture; double-poly triple-metal process; multi-bit ADC; switched-capacitor architecture; Attenuation; Bandwidth; CMOS process; Capacitors; Energy consumption; Feedback; MOS devices; Pipelines; Switches; Switching circuits;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912575
