A 80/20 MHz 160 mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications

Author

Chi-Weon Yoon ; Woo, R. ; Jeonghoon Kook ; Se-Joong Lee ; Langmin Lee ; Young-Don Bae ; In-Cheol Park ; Hoi-Jun Yoo

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

142

Lastpage

143

Abstract

An 84 mm/sup 2/ 160 mW programmable processor in 0.18 /spl mu/m EMC technology consists of 32 b RISC with MAC, 20 MHz motion compensation accelerator for MPEG-4 at SP, 3D rendering engine with 2.2 M polygon/s at 20 MHz, and 7.125 Mb embedded DRAM with single bitline writing scheme.

Keywords

digital signal processing chips; motion compensation; multimedia computing; pipeline processing; reduced instruction set computing; rendering (computer graphics); 0.18 micron; 160 mW; 20 MHz; 32 bit; 3D rendering engine; 80 MHz; EMC technology; MAC; RISC; embedded DRAM MPEG-4 accelerator; motion compensation accelerator; multimedia processor; single bitline writing scheme; Bandwidth; Data processing; Engines; Equalizers; Hardware; MPEG 4 Standard; Motion compensation; Pipelines; Random access memory; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912578

Filename

912578