Timing based DWT approach for at-speed capture power reduction

Modern technology applications are constantly demanding ultra low power integrated circuit (IC) design. The testing of these low-power devices are considered as one of the most important challenge in semiconductor industry [2, 3, 4, 5]. This paper provides a path timing based design with test (DWT) approach for limiting the power during test capture phase. The motive is to introduce some sort of logic into the net list during synthesis itself to disassociate the at-speed testing of critical paths from that of the non-critical ones. In other words, during critical paths at-speed testing, the logic passes on the second edge of the capture clock only to the flops at the end-points of timing critical paths and not to the flops at the endpoints of non timing critical paths. Also the flip-flops outputs which are going only to the non critical logic paths are gated during the entire capture cycle so that overall switching is minimized. This proposed solution is experimented on an encryption sub block design and this approach reduces the capture peak power up to 45% compared to the original design. This approach allows the test engineer to have a better control over the overall peak power consumption during at speed test.