Design challenges of voltage multiplier in a 0.35-μm 2-poly 4-metal CMOS technology for RFID passive tags

Author

Lo, Hiu Yeung ; Or, Pui Ying ; Leung, Ka Nang ; Leung, Lai Kan ; Choy, Chiu Sing ; Pun, Kong Pang

Author_Institution

Chinese Univ. of Hong Kong, Shatin

fYear

2007

fDate

20-22 Dec. 2007

Firstpage

433

Lastpage

436

Abstract

A voltage multiplier for passive RFID tags is designed in a 0.35-μm 2-poly 4-metal CMOS technology. Due to the limitations of the technology, an optimized design is difficult to achieve easily. Based on some design studies, an voltage multiplier working at 13.5 MHz is developed and realized on silicon. From the measurement, the output voltage is about 2.5 V and the output current is 6.4 μA. when an input AC signal of 1.5 V_pp is applied. Circuit simulation shows that the power efficiency can be 16.25% in the optimized case.

Keywords

CMOS integrated circuits; circuit simulation; integrated circuit design; low-power electronics; metals; radiofrequency identification; silicon; voltage multipliers; RFID passive tags; circuit simulation; current 6.4 μA; design challenges; frequency 13.5 MHz; metal CMOS; silicon; size 0.35 μm; voltage 1.5 V; voltage 2.5 V; voltage multiplier; Active RFID tags; CMOS technology; Charge pumps; Design optimization; MOSFET circuits; Passive RFID tags; Radiofrequency identification; Schottky diodes; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Conference_Location

Tainan

Print_ISBN

978-1-4244-0636-4

Electronic_ISBN

978-1-4244-0637-1

Type

conf

DOI

10.1109/EDSSC.2007.4450155

Filename

4450155