Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

Author

Osada, K. ; Jin-Uk Shin ; Khan, M. ; Yu-De Liou ; Wang, K. ; Shoji, K. ; Kuroda, K. ; Ikeda, S. ; Ishibashi, K.

Author_Institution

Hitachi Semicond. America Inc., San Jose, CA, USA

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

168

Lastpage

169

Abstract

This 32 kB cache design operates from 120 MHz at 1.7 mW and 0.65V to 1.04 GHz at 530 mW and 2.0 V with a single internal supply using 0.18 /spl mu/m CMOS technology. The wide voltage operating range is achieved using a voltage-adapted timing-generation scheme with plural dummy cells and a lithographically-symmetric cell (LS-cell).

Keywords

CMOS memory circuits; cache storage; cellular arrays; timing; 0.18 micron; 0.65 to 2.0 V; 1.7 to 530 mW; 120 MHz to 1.04 GHz; 32 kB; CMOS technology; cache; lithographically-symmetric cell; plural dummy cells; single internal supply; voltage-adapted timing-generation scheme; wide voltage operating range; CMOS technology; Circuit testing; Fluctuations; Frequency; Low voltage; Optical amplifiers; Pulse amplifiers; Random access memory; Threshold voltage; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912589

Filename

912589

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2982018