Compound Semiconductor as CMOS Channel Material: DéjÃ\xa0 vu or New Paradigm?

We have examined the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25 V supply voltage (V_CC). Based on the two-dimensional numerical drift-diffusion simulations, we conclude that 30 nm gate length InAs (indium arsenide) based TFETs can achieve I_on/I_off of > 4x10⁴ with < 1 ps intrinsic delay at 0.25 V V_CC. In fact, the InAs TFETs show the maximum benefit when their supply voltage V_CC is scaled aggressively down to 0.25 V and this benefit primarily arises from a) efficient tunneling under low electric field and b) their higher source-side injection velocity. MOSFETs or quantum-well FETs in this low V_DD range do not even meet the I_on-I_off stipulation of 10⁴.