DocumentCode
2982633
Title
Physical design of a fourth-generation POWER GHz microprocessor
Author
Anderson, C.J. ; Petrovick, J. ; Keaty, J.M. ; Warnock, J. ; Nussbaum, G. ; Tendier, J.M. ; Carter, C. ; Chu, S. ; Clabes, J. ; DiLullo, J. ; Dudley, P. ; Harvey, P. ; Krauter, B. ; LeBlanc, J. ; Pong-Fei Lu ; McCredie, B. ; Plum, G. ; Restle, P.J. ; Runy
Author_Institution
IBM Corp., Austin, TX, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
232
Lastpage
233
Abstract
The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.
Keywords
cache storage; integrated circuit interconnections; microprocessor chips; silicon-on-insulator; 0.18 micron; 1.1 GHz; 1.5 V; 115 W; SOI technology; Si; fourth-generation POWER GHz microprocessor; interconnect; microprocessor cores; multiple chips; off-chip L3; shared L2; CMOS technology; Capacitance; Circuit testing; Circuit topology; Clocks; Contracts; Laboratories; Microprocessors; Timing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912617
Filename
912617
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