• DocumentCode
    2982653
  • Title

    Impact of Source/Drain Tie on a 30 nm Bottom Gate MOSFETs

  • Author

    Lin, Jyi-Tsong ; Lin, Jeng-Da ; Shiang-Shi, Kang ; Huang, Hau-Yuan ; Kao, Kung-Kai ; Eng, Yi-Chuen

  • Author_Institution
    Nat. Sun Yat-Sen Univ., Kaohsiung
  • fYear
    2007
  • fDate
    20-22 Dec. 2007
  • Firstpage
    585
  • Lastpage
    588
  • Abstract
    This paper presents a non-classical architecture called the bottom gate MOSFET with source/drain tie (S/D-tied BG) to achieve enhanced device reliability. According to the 2-D numerical simulation, the proposed structure can effectively reduce the effects of self-heating because of its source/drain-tied scheme, resulting in improved thermal stability. In addition, S/D-tied BG MOSFET not only diminishes short-channel effects but also decreases source/drain series resistance, which is the major advantage over the conventional ultra-thin SOI.
  • Keywords
    MOSFET; numerical analysis; semiconductor device reliability; 2D numerical simulation; bottom gate MOSFET; device reliability; self-heating; series resistance; short-channel effects; size 30 nm; source/drain-tied scheme; thermal stability; Degradation; Dry etching; Electron beams; Immune system; Lithography; MOSFETs; Numerical simulation; Planarization; Silicon; Thermal stability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
  • Conference_Location
    Tainan
  • Print_ISBN
    978-1-4244-0637-1
  • Electronic_ISBN
    978-1-4244-0637-1
  • Type

    conf

  • DOI
    10.1109/EDSSC.2007.4450192
  • Filename
    4450192