First-generation MAJC dual microprocessor

Author

Kowalczyk, A. ; Adler, V. ; Amir, C. ; Chiu, F. ; Choon Chug ; De Lange, W. ; Dubler, S. ; Yuefei Ge ; Ghosh, S. ; Tan Hoang ; Hu, R. ; Baoqing Huang ; Kant, S. ; Kao, Y.S. ; Cong Khieu ; Kumar, S. ; Chung Lau ; Lan Lee ; Liebermensch, A. ; Xin Liu ; Malu

Author_Institution

Sun Microsyst. Inc., Palo Alto, CA, USA

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

236

Lastpage

237

Abstract

The MAJC 5200 is a dual 32b microprocessor system-on-a-chip, utilizing 0.22 /spl mu/m CMOS with all-Cu interconnect. Two CPUs, delivering GGFLOPS and 13GOPS at 500 MHz, are tightly coupled through a shared, coherent, 4-way set associative 16 KB data cache, and an on-chip 4 GB/s switch. Each CPU is a 4-issue VLIW engine.

Keywords

CMOS digital integrated circuits; application specific integrated circuits; cache storage; content-addressable storage; instruction sets; microprocessor chips; parallel architectures; 0.22 micron; 16 KB; 32 bit; 4 GB/s; 500 MHz; CMOS; MAJC 5200; dual microprocessor system-on-a-chip; four-issue VLIW engine; four-way set associative data cache; on-chip switch; Clocks; Delay; Flip-flops; Integrated circuit interconnections; Microprocessors; Pipelines; Random access memory; Switches; Temperature measurement; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912619

Filename

912619