Title :
A timing-driven global router for custom chip design
Author :
Prasitjutrakul, S. ; Kubitz, W.J.
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
A timing-driven global router is presented for custom chip design, whose objective is maximizing the minimum delay slack. Resistances and capacitances of interconnections, input gate capacitances and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computed interconnection delays is used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is comparable to the output-driver resistance, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm presented is experimentally shown to produce global routes achieving the objective.<>
Keywords :
application specific integrated circuits; circuit layout CAD; delays; custom chip design; input gate capacitances; minimum delay slack; multiterminal net; output driver resistance; timing-driven global router; Capacitance; Chip scale packaging; Closed-form solution; Delay effects; Delay estimation; Integrated circuit interconnections; Pins; Routing; Timing; Wire;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129837