Title :
A 6.25 Gb/s Decision Feedback Equalizer used in SerDes for High-speed Backplane Communications
Author :
Zhou, Mingzhu ; Zhu, En ; Wang, Shoujun ; Wang, Zhigong
Author_Institution :
Southeast Univ., Nanjing
Abstract :
A 6.25 Gb/s two-tap DFE (decision feedback equalizer) in high-speed backplane receiver has been designed in a 0.18-mum CMOS. The pipelined architecture in the half-rate DFE achieves an increase in the transmitted data rate over conventional DFE with a small increase in area. Near end data is a 6.25 Gb/s PRBS10 with 0.5 Vp-p, and the DFE recovered data has been measured with jitter (pp) of 3 ps and a horizontal eye-opening of 0.97 UI, a vertical eye opening of 0.48 V.
Keywords :
CMOS analogue integrated circuits; decision feedback equalisers; high-speed integrated circuits; microwave integrated circuits; microwave receivers; CMOS design; SerDes; bit rate 6.25 Gbit/s; decision feedback equalizer; high-speed backplane communications; high-speed backplane receiver; pipelined architecture; size 0.18 mum; time 3 ps; voltage 0.48 V; Backplanes; Communication systems; Data communication; Decision feedback equalizers; Ethernet networks; Frequency response; Intersymbol interference; Jitter; Modems; Transmitters;
Conference_Titel :
Microwave and Millimeter Wave Technology, 2007. ICMMT '07. International Conference on
Conference_Location :
Builin
Print_ISBN :
1-4244-1049-5
Electronic_ISBN :
1-4244-1049-5
DOI :
10.1109/ICMMT.2007.381426
