Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip

Author

Burns, J. ; McIlrath, L. ; Keast, C. ; Lewis, C. ; Loomis, A. ; Warner, K. ; Wyatt, P.

Author_Institution

Lincoln Lab., MIT, Lexington, MA, USA

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

268

Lastpage

269

Abstract

Shows the feasibility of stacking SOI circuits to build 3D-ICs with dense vertical interconnects; the results are being applied to develop higher performance systems. Low-power circuits with three metal levels are fabricated with a 0.25/spl mu/m fully-depleted SOI technology. Three or more circuit layers are stacked and connected with 3D vias whose size, pitch, and resistance will be decreased by replacing the adhesive process with low temperature oxide bonding and utilizing tungsten plugs to fill high-aspect-ratio vias.

Keywords

adhesion; application specific integrated circuits; integrated circuit interconnections; silicon-on-insulator; 0.25 micron; 3D vias; SOI circuits; Si; adhesive process; dense vertical interconnects; fully-depleted SOI technology; high-aspect-ratio vias; high-bandwidth systems on a chip; low temperature oxide bonding; low-power circuits; metal levels; pitch; resistance; size; three-dimensional integrated circuits; tungsten plugs; Assembly; Etching; Integrated circuit interconnections; Inverters; Ring oscillators; Sensor arrays; Sensor phenomena and characterization; Silicon; Three-dimensional integrated circuits; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912632

Filename

912632