Design of High-speed CMOS Frequency Dividers for RF Receiver

Author

Tang, Lu ; Wang, Zhi-Gong ; He, Xiao-Hu ; Li, Zhi-qun ; Xu, Yong

Author_Institution

Southeast Univ., Nanjing

fYear

2007

fDate

18-21 April 2007

Firstpage

1

Lastpage

4

Abstract

A divide-by-16/17 dual-modulus prescaler (DMP) and two programmable & plus swallow dividers for application in a digital video broadcasting-terrestrial (DVB-T) receiver are designed in a 0.18mum 3.3V mixed-signal CMOS process. The master/slave D-flip-flop (DFF) in the DMP is made up of an improved D-latch to increase the speed and the driving capability. A novel D-latch architecture integrated with ´OR´ logic is proposed to decrease the complexity of the circuit. Post simulation results of the chip layout indicate that the proposed DMP works well at the frequency band of 1~2 GHz. The maximum operating speed is 2.4 GHz. The programmable & plus swallow dividers are directly synthesized by EDA tools and finally fabricated with 0.18 mum standard library.

Keywords

CMOS integrated circuits; UHF integrated circuits; flip-flops; frequency dividers; radio receivers; D-latch architecture; DVB-T; RF receiver; digital video broadcasting-terrestrial receiver; dual-modulus prescaler; frequency 1 GHz to 2 GHz; high-speed CMOS frequency dividers; master-slave D-flip-flop; mixed-signal CMOS process; CMOS logic circuits; CMOS process; Circuit simulation; Digital video broadcasting; Electronic design automation and methodology; Frequency conversion; Integrated circuit synthesis; Logic circuits; Master-slave; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology, 2007. ICMMT '07. International Conference on

Conference_Location

Builin

Print_ISBN

1-4244-1049-5

Electronic_ISBN

1-4244-1049-5

Type

conf

DOI

10.1109/ICMMT.2007.381430

Filename

4266189