Title :
Testability guided BIST technique
Author :
Fang, Yu ; Albicki, Alexander
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
Abstract :
In this paper, a novel Built-In-Self-Test (BIST) scheme is presented. It transforms the circuit into an easily testable entity under the guidance of random pattern testability analysis, and subsequently performs pseudo-random test pattern generation and signature analysis. Experiments on ISCAS85 benchmark circuits show that this scheme helps to achieve higher efficiency in random pattern testing
Keywords :
built-in self test; design for testability; integrated circuit testing; logic design; logic testing; built-in-self-test scheme; pseudo-random test pattern generation; random pattern testability analysis; signature analysis; testability guided BIST technique; Benchmark testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Controllability; Fault detection; Observability; Pattern analysis; Performance analysis;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519224
