On concurrent error detection of finite state machine systems

This paper addresses the issue of using built-in hardware logic to ensure correct operation of hard-wired control units (e.g. PLA-based finite state machines). The proposed technique checks the signature of a group of sequential slates bounded by special predefined states in the finite state machine. This on-line error detection scheme provides real time detection of faults once they occur. The finite state machine (FSM) is decomposed into separate fragments. A key (a bit pattern) is assigned In every fragment of the FSM corresponding to the correct sequence of output (or slates). The control flow is then checked by comparing the current values of the key sequence obtained during the algorithm execution with a reference key previously calculated corresponding to fault-free operation of the FSM