Design of Radix 4 SRT Dividers for Single Precision DSP in Deep Submicron CMOS Technology

This paper presents a proposal for design of radix 4 SRT dividers for single precision DSP in deep submicron CMOS technology. Radix 4 dividers with minimal redundancy were used widely in the previous technologies where minimizing the die area was the top priority. This was done because these dividers only require simple multiples of divisor, and quotient conversion was typically done by on-the-fly conversion without the need for an adder. On the other hand, in the current deep submicron CMOS technology where many millions of transistors are available in a relatively small silicon area, it is attractive to use an adder and maximum redundancy to simplify quotient selection and conversion. Replacing the on-the-fly conversion that operates on every cycle by an adder that operates only one cycle reduces the switching factor by the order of 6x. This is significant because the on-the-fly conversion can consume 30% of the total energy of a divider. Furthermore, thanks to the elimination of the big lookup table intrinsic in minimally redundant SRT dividers, the quotient computation is sped up. To illustrate this concept of trading a little extra hardware for reduced power and increased speed in the deep submicron CMOS technology, a number of single precision radix 4 dividers with maximal redundancy are designed and implemented in 65 nm CMOS technology using an ASIC flow and triple VT devices. Clock and data gating and data recirculating techniques are used to save power. High VT devices are introduced to reduce leakage power. Finally, a novel method to evaluate different alternatives for energy efficiency is described along with the implementation results