A DSP based receiver for 1000BASE-T PHY

The IEEE Standard 802.ab 1000BASE-T specifies the physical layer (PHY) for Gigabit Ethernet over CAT-5 cabling systems. Operating over the widely-deployed CAT-5 cabling systems currently used for 100BASE-TX, 1000BASE-T provides a smooth way to increase the data rate by ten times over 100BASE-TX. For every incoming data byte, the trellis encoder outputs four PAM-5 symbols to four pairs of wires at 125 MBaud/s. The trellis code has an eight-state radix-4 trellis, it provides 6 dB coding gain for an ISI free channel. In practice, the gain could be less than 6 dB due to the ISI. Signals are transmitted on both directions on each of the four wires, therefore, echo must be removed on each wire. In addition, near-end cross-talk (NEXT) can also be removed in a way similar to removal of echo cancellation. The architectural features of a 0.18 /spl mu/m CMOS IC implementing the 1000BASE-T PHY are presented here. Decision feedback equalization (DFE) removes ISI.