Title :
Testing and simulation of degrading faults
Author :
Abujbara, Hussam Y. ; Al-Arian, Sami A.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
Fault degrading is the result of a defect mechanism which has no effect on the logical behavior of the circuit, but rather causes performance degradation to the circuit. This degradation is manifested in poor signal propagation delays, and weak noise immunity. However, there are no testing techniques and no fault models that are capable of handling the testing of the degrading fault by using digital fault simulation. A defect model that is capable of mapping degrading defects syndrome into a Boolean behavior (syndrome) would make it possible to use higher speed digital fault simulation techniques, rather than analog parametric testing. This approach for testing is more reliable and would cover both; degrading faults (DF) and fatal (catastrophic) faults (CF) in the system
Keywords :
built-in self test; delays; fault diagnosis; logic testing; timing; BIST; Boolean behavior; catastrophic faults; defect model; degrading defects syndrome; degrading fault simulation; degrading fault testing; gate delay model; multiple transition detection; noise immunity; nonrobust fault simulation; path delay model; performance degradation; robust fault simulation; signal propagation delays; single transition test; Circuit faults; Circuit noise; Circuit simulation; Circuit testing; Computational modeling; Computer science; Degradation; Propagation delay; Robustness; System testing;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519231
