Design of C-testable high-speed dividers

This paper presents a design of a C-testable carry-free divider circuit and its test generation. The divider circuit takes the dividend and divisor digits, in redundant binary form, as its inputs and produces the quotient and remainder digits, also in redundant binary form. The circuit is fully testable with a test set of 72 test patterns irrespective of its bit size. In order to easily generate the test patterns and the corresponding control signals, a graph labeling scheme is employed to derive a set of simple labels for the dividend, the divisor the quotient, the remainder, and the control signals