DocumentCode
298334
Title
A rule-based approach for high speed adders design verification
Author
Elleithy, Khaled M. ; Aref, Mostafa A.
Author_Institution
Coll. of Comput. Sci. & Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Volume
1
fYear
1994
fDate
3-5 Aug 1994
Firstpage
274
Abstract
In this paper, a rule-based framework for formal hardware verification is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). The environment supports verification at different levels of hardware specification. The rule-based framework has been tested on the design of high speed adders
Keywords
adders; circuit analysis computing; digital arithmetic; digital integrated circuits; formal verification; integrated logic circuits; knowledge based systems; logic CAD; theorem proving; C Language Integrated Production System; CLIPS; PROVER system; adders design verification; formal hardware verification; high speed adders; rule-based framework; Formal verification; Hardware; Large-scale systems; Libraries; Logic; Microprocessors; Production systems; Specification languages; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location
Lafayette, LA
Print_ISBN
0-7803-2428-5
Type
conf
DOI
10.1109/MWSCAS.1994.519238
Filename
519238
Link To Document