DAC topologies for GSM ΣΔ modulators

Multi-bit ΣΔ modulators have become the preferred option for high performance, low power cellular GSM applications. When using multi-bit quantization, modulator performance becomes extremely sensitive to the internal digital-to-analog converter (DAC) non-linearity. DAC designs must fulfill linearity, power, and speed requirements for GSM while at the same time enabling dynamic element matching (DEM) techniques to further alleviate linearity problems. In this paper, four architectures are analyzed as candidate DACs for a fully differential (FD), GSM, SDM design. Our analysis highlights the advantages of an FD Charge redistribution DAC (CDAC) topology that uses individual level averaging (ILA) as DEM. Simulations favor a CDAC architecture mainly because it provides the best speed/power/linearity compromise. Evaluations of a complete modulator design using the proposed FD CDAC topology were performed, showing that no in-band harmonic distortion is present in the modulator output.