Sub-500 ps 64 b ALUs in 0.18 /spl mu/m SOI/bulk CMOS: Design & scaling trends

The requirements of high-throughput Internet servers necessitate the use of multiple ALUs in high-performance 64 b execution cores. Consequently, each ALU demands a compact, energy-efficient 64 b adder core with single-cycle latency. The resultant critical path, which is a balanced mix of interconnect, diffusion and gate loads, forms a representative test bed for evaluating competing circuit techniques and process technologies (bulk CMOS/SOI). This paper presents: (i) the design of an energy-efficient 64 b ALU in 0.18 /spl mu/m bulk CMOS technology; (ii) a direct port of this design to a comparable SOI technology and (iii) an SOI-optimal redesign of the adder core. Further, it describes design margining required for the SOI implementations and reports the results of shrinking the two architectures to 0.13 /spl mu/m Bulk/SOI. In both cases, a sophisticated SOI compact model that incorporates features to effectively model the SOI floating body effect is used.