Title :
A 1 GHz PA-RISC processor
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
The processor is a leveraged design based of a previous generation of PA-RISC processor. Key improvements over the previous design are: a 0.18 /spl mu/m silicon on insulator (SOI) process with 7-layer copper interconnects, 2.25 MB of Cache with row and column redundancies, 240-entry translation lookaside buffer (TLB), 60% frequency boost, and 45% lower power with the same foot print.
Keywords :
microprocessor chips; reduced instruction set computing; silicon-on-insulator; 0.18 micron; 1 GHz; 2.25 MB; Cu; PA-RISC processor; SOI process; cache memory; multilayer copper interconnect; redundancy; translation lookaside buffer; Clocks; Gate leakage; Integrated circuit interconnections; Latches; Parasitic capacitance; Routing; Switches; Testing; Threshold voltage; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912657
