• DocumentCode
    298355
  • Title

    VSDF: synchronous data flow for VLSI

  • Author

    Kerihuel, Alain ; McConnell, Roderick ; Rajopadhye, Sanjay

  • Author_Institution
    IRISA, Rennes, France
  • Volume
    1
  • fYear
    1994
  • fDate
    3-5 Aug 1994
  • Firstpage
    389
  • Abstract
    This article describes a modified Synchronous Data Flow (SDF) model which is suitable for modeling synchronous VLSI circuits. The target model takes advantage of the synchronous nature of the operations to eliminate buffering between circuits where possible. We introduce a temporal notation, and define relevant functions for constructing a system
  • Keywords
    VLSI; circuit CAD; data flow graphs; digital integrated circuits; integrated circuit modelling; logic CAD; synchronisation; IC modelling; synchronous VLSI circuits; synchronous data flow model; Clocks; Delay; Discrete cosine transforms; Equations; Large scale integration; Logic circuits; Quantization; Telecommunication standards; Transform coding; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
  • Conference_Location
    Lafayette, LA
  • Print_ISBN
    0-7803-2428-5
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1994.519263
  • Filename
    519263
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=298355