Feasibility region modeling of analog circuits for hierarchical circuit design

Author

Shao, Jianfeng ; Harjani, Ramesh

Author_Institution

Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

Volume

1

fYear

1994

fDate

3-5 Aug 1994

Firstpage

407

Abstract

During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. In this paper we concentrate on techniques to model the feasibility region. The methodology is general and can be used for both analog and digital circuits. Macromodels are developed and verified for analog blocks at different levels of hierarchy

Keywords

analogue integrated circuits; circuit CAD; integrated circuit design; integrated circuit modelling; mixed analogue-digital integrated circuits; CAD; analog circuits; digital circuits; feasibility region modeling; hierarchical circuit design; macromodels; mixed-mode ASICs; sub-block design feasibility; Analog circuits; Circuit synthesis; Digital circuits; Manufacturing processes; Process design; Stress; Tail; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519267

Filename

519267