DocumentCode
298381
Title
Integrated circuit for Hamming neural net
Author
Gomez-Castaneda, Felipe ; Moreno-Cadenas, Jose
Author_Institution
Dept. of Electr. Eng., Center for Res & Adv. Studies of the IPN, Mexico City, Mexico
Volume
1
fYear
1994
fDate
3-5 Aug 1994
Firstpage
515
Abstract
The authors describe a CMOS integrated circuit in 2-micron, n-well technology for performing the parallel analog computation of a specific Hamming neural net. This electrical network supports a full digital feature at its output terminals derived from a self excitatory mechanism in the competing WTA units. Details are given of the transient response by PSpice simulations
Keywords
CMOS analogue integrated circuits; analogue processing circuits; neural chips; parallel processing; transient analysis; transient response; 2 micron; CMOS integrated circuit; Hamming neural net; PSpice simulations; WTA units; n-well technology; parallel analog computation; self excitatory mechanism; transient response; CMOS integrated circuits; CMOS technology; Cities and towns; Computer architecture; Concurrent computing; Error correction; Neural networks; Silicon; Steady-state; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location
Lafayette, LA
Print_ISBN
0-7803-2428-5
Type
conf
DOI
10.1109/MWSCAS.1994.519291
Filename
519291
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