Title :
Optimization of the parallel technique for compiled unit-delay simulation
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
The parallel technique is a purely compiled method for unit-delay simulation that is based on levelized compiled simulation and bit parallel simulation. The parallel technique provides rapid simulations with a reasonable amount of code, but there are opportunities for optimization. The author presents two schemes: bit-field trimming and shift-elimination. Performance results are presented that demonstrate an average performance improvement of 47%.<>
Keywords :
logic CAD; optimisation; bit-field trimming; compiled unit-delay simulation; optimisation; parallel technique; performance; shift-elimination; Analytical models; Circuit simulation; Computational modeling; Computer science; Delay effects; Discrete event simulation; History; Propagation delay; Testing; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129843
