A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture

A 1.8 V 4 Gb DDR SDRAM for low voltage and high speed at full density has reduced inter-bitline coupling noise in the twisted open bit line architecture. Amplifier sensitivity and sensing margin are improved by gain-controlled pre-sensing and active calibration of the bitline reference voltage. For noise-immune power-stabilized operation, three circuit schemes suitable for the SDRAM are presented: (i) twisted open bitline (TOB) architecture; (ii) gain-controlled pre-sensing (GCP); and (iii) reference bitline calibration (RBC). The TOB scheme eliminates the coupling noise between adjacent BLs by holding neighboring bitlines stable at the reference voltage with the open readout and sensing using a reference BL from the adjacent block. The GCP scheme increases the sensing margin and speed by employing transconductance-matched pre-amplification. The RBC scheme actively mimics the cell data retention characteristics and yields an optimal voltage level for the reference BL from the charge-shared voltage from replica BL pairs. Together with a chip-size-efficient core signal repeating architecture, these schemes ensure reliable low-voltage and high-speed cell and core operation.