DocumentCode
2984047
Title
A 1.43 GHz per data I/O 16 Mb DDR low-power embedded DRAM macro for a 3D graphics engine
Author
Hardee, K. ; Jones, O.F. ; Parris, M. ; Butler, D. ; Aldrich, L. ; Austin, P. ; Jacobsen, K. ; Miyabayashi, M. ; Taniguchi, K. ; Arakawa, T.
Author_Institution
United Memories Inc., Colorado Springs, CO, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
386
Lastpage
387
Abstract
This 16 Mb embedded DRAM macro is optimized for use in a 3D graphics engine chip. The main characteristics of this macro are a 714 MHz clock, 1.43 GHz per I/O data rate (DDR), and reduced power (520 mW at 1.5 V). Additional features include a hidden write mode and low-capacitance, low-power data busing.
Keywords
computer graphic equipment; high-speed integrated circuits; integrated memory circuits; low-power electronics; random-access storage; 1.43 GHz; 1.5 V; 16 Mbit; 3D graphics engine; 3D graphics engine chip; 520 mW; 714 MHz; DDR DRAM macro; hidden write mode; low-capacitance data busing; low-power data busing; low-power embedded DRAM macro; Capacitance; Clocks; Driver circuits; Engines; Graphics; Jacobian matrices; Logic; Random access memory; Read-write memory; Springs;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912685
Filename
912685
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