A 4 GHz 40 dB PSRR PLL for an SOC application

This PLL achieves >40dB power-supply-rejection ratio (PSRR) operating at 4GHz. The PLL is for use in a high-speed SOC that operates at internal clock frequencies exceeding 2GHz. The high level of noise rejection is achieved with a high-bandwidth voltage regulator that provides a nominally noise-free 2.OV supply to the PLL sensitive analog blocks. Previous PLL designs employ voltage regulators to filter out supply noise but generally are limited to PSRRs <25dB. The regulator is powered using the SOC 3.3V I/O power supply.