• DocumentCode
    2984124
  • Title

    Low Cost and Low Jitter DDS-Like Frequency Synthesizer

  • Author

    Chen, Hsin-Chuan

  • Author_Institution
    St. John´´s Univ., Tainan
  • fYear
    2007
  • fDate
    20-22 Dec. 2007
  • Firstpage
    897
  • Lastpage
    900
  • Abstract
    Reconfigurable clock is necessary for many applications such as digital communication systems, however, using the conventional direct digital frequency synthesizer (DDS) as a pulse or clock generator may cause jitter problems. People usually employ phase-interpolation approaches to generate a pulse or clock with correct time intervals. In this paper, a DDS-like frequency synthesizer without phase accumulator is proposed, which only uses the single capacitor integration to directly achieve the clock output with the same time intervals, such that the delay generator within phase interpolation is unnecessary. Therefore, the proposed DDS-like frequency synthesizer using single capacitor integration can significantly reduce much hardware complexity, and it also obtains a low phase jitter clock output.
  • Keywords
    clocks; direct digital synthesis; jitter; direct digital frequency synthesizer; jitter; phase-interpolation; reconfigurable clock; Capacitors; Clocks; Costs; Delay effects; Digital communication; Frequency synthesizers; Hardware; Interpolation; Jitter; Pulse generation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
  • Conference_Location
    Tainan
  • Print_ISBN
    978-1-4244-0637-1
  • Electronic_ISBN
    978-1-4244-0637-1
  • Type

    conf

  • DOI
    10.1109/EDSSC.2007.4450270
  • Filename
    4450270