Title :
Error Analysis of Integrated Resistor Attenuation Network
Author :
Zheying, Li ; Limei, Xiu ; Jia, Liu ; Chaisia, Lv ; Shuo, Li
Author_Institution :
Inst. of Micro Electron. Applic. Technol., Beijing Union Univ., Beijing, China
Abstract :
The model and synthesis method of integrated linear attenuation network (LAC) used in mixed signal SoC for digital instrument are addressed in this paper. The model and synthesis method of the LAC used for electronics instrument is related with the application and implementation method. To the signal generator used in some electronics instrument, the LAC architecture could be linear and synthesized by resistor network and some additional circuits. Therefore, the spectrum properties of the LAC are relayed on the spectrum properties of additional circuits. The synthesis method is derived the formula of the LAC model. With the model, the integrated resistor network in the LAC used for measurement circuit module could be reduced. The LAC architecture synthesis method is suitable for the application of implementing a LAC with integrated circuit technology.
Keywords :
active networks; attenuation measurement; digital instrumentation; error analysis; linear network synthesis; mixed analogue-digital integrated circuits; passive networks; resistors; system-on-chip; voltage measurement; LAC; active attenuation network; digital instrument; electronics instrument; error analysis; integrated linear attenuation network; measurement circuit module; mixed signal SoC; passive attenuation network; Attenuation; Bismuth; Equations; MOSFETs; Mathematical model; Resistors; System-on-a-chip; Embedded technology; SoC; instrument;
Conference_Titel :
Electrical and Control Engineering (ICECE), 2010 International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-6880-5
DOI :
10.1109/iCECE.2010.906
