• DocumentCode
    2984360
  • Title

    The circuit with valley switching technique

  • Author

    Liang, Sun ; Si, Chen ; Xiaobo, Wu ; Xiaolang, Yan

  • Author_Institution
    Zhejiang Univ., Hangzhou
  • fYear
    2007
  • fDate
    20-22 Dec. 2007
  • Firstpage
    941
  • Lastpage
    943
  • Abstract
    To implement soft switching in power management integrated circuit, a valley switching technique was proposed in this paper. Valley switching technique can significantly reduce the switching losses by discharging the parasitical capacitor across MOSFET before the switch is turned on. In order to improve the precision of valley detection, a principle of modulating hysteretic window was proposed to reduce the delay. The practical circuit was analyzed and simulated to verify this approach. The results showed that the performance of the circuit is consistent with expectations well.
  • Keywords
    MOSFET; capacitors; switching circuits; MOSFET; parasitical capacitor; power management integrated circuit; soft switching; valley switching technique; Analytical models; Capacitors; Circuit analysis; Delay; Energy management; Hysteresis; MOSFET circuits; Switches; Switching circuits; Switching loss;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
  • Conference_Location
    Tainan
  • Print_ISBN
    978-1-4244-0637-1
  • Electronic_ISBN
    978-1-4244-0637-1
  • Type

    conf

  • DOI
    10.1109/EDSSC.2007.4450281
  • Filename
    4450281