Secure hardware design through bit-tight information flow control

Hardware designers tend to focus more on function correctness and performance parameters of the system than information security. As a result, hardware devices are disclosing confidential information through system side effects, which is vulnerable to attackers. Unfortunately, conventional security countermeasures such as encryption algorithms and access control mechanisms are inefficient in preventing information leakage through hard-to-detect covert channels. Recently, gate level information flow tracking (GLIFT) has been proposed to monitor all digital information flows in the underlying hardware and prevent information leakage caused by undesired interference between different hardware components. However, existing work in this realm restricts to combinational logic, which is not applicable for sequential circuits. This paper extends the GLIFT method to sequential logic and presents various methodologies for secure hardware design by enforcing bit-tight information flow control. Finally, experiments are conducted to evaluate area and performance overheads of the GLIFT method using sequential benchmarks.