Title :
A 6.0-GHz Low Noise Amplifier and A 6.0-GHz Class-E Power Amplifier
Author :
Yang, Hsin-Chia ; Chen, Po-Yu ; Wang, Chuei-Tang
Author_Institution :
Ming Hsin Univ. of Sci. & Technol., Hsinchu
Abstract :
-Devices using 0.18mum CMOS process are used to design radio frequency amplifiers, a 6.0-GHz low noise amplifier (LNA) and an 6.0-GHz Class-E power amplifier. The LNA, with input power Pin=10.38mW, input voltage Vdd=1.5V, and input current Id=6.92mA, provides a forward gain S21=32.135 dB with a Noise Figure as low as 1.0dB. In addition, a 6.0 GHz E-class amplifier, with input voltage Vdd=1.5V, provides a forward gain S21=22.374dB with Pout=7.136 dBm and power added efficiency PAE = 76.1%. Both amplifiers are to be checked on the architecture and linearity for comparison. Class-E power amplifiers with different center frequencies are to be presented and their corresponding S21´s are checked, too.
Keywords :
CMOS analogue integrated circuits; low noise amplifiers; power amplifiers; CMOS process; class-E power amplifier; frequency 6.0 GHz; low noise amplifier; radio frequency amplifier; size 0.18 micron; CMOS process; Capacitors; Circuit synthesis; Frequency; Linearity; Low-noise amplifiers; Noise figure; Power amplifiers; Radiofrequency amplifiers; Voltage; Low noise amplifiers (LNA); class-E power amplifiers (PA); noise figure (NF); power added efficiency (PAE);
Conference_Titel :
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-0637-1
Electronic_ISBN :
978-1-4244-0637-1
DOI :
10.1109/EDSSC.2007.4450297
