Reliability of 100 nm silicon nitride capacitors in an InP HEMT MMIC process

A reliability study has been conducted on capacitors made with 100 nm of silicon nitride, in an InP HEMT MMIC fabrication process. Special wafers were fabricated, containing 1482 200 μm×200 μm capacitors each, and these were probed automatically. They were subject to ramped-voltage stress and the breakdown voltages recorded. On a typical wafer the vast majority of the breakdown voltages are between 50 and 90 V. In addition, I-V curves were measured on a small number of specimens from 0 V up to breakdown. This was done in two regimes: above 25 V with a conventional setup, and below 25 V with an ultra-low-current measurement system. These were done at 25°C and 175°C above 25 V, and at 25°C only below 25 V. These were fitted well with a model for the conductivity, consisting of an ohmic conduction at low voltages and Frenkel-Poole conduction at high voltages. Parameters of the fits included thermal activation energies, the voltage acceleration factor in the Frenkel-Poole model, and d_eff, the effective thickness of the dielectric at the thinnest point. Analysis invoked the time-dependent dielectric breakdown model, which provides the time to failure as a function of the deff, while deff can be found from the ramped-voltage measurements. From the 10 wafers that have been probed so far, the mean of the distribution of failure times (at 1.5 V, 40°C) is above 5×10⁷ hrs, and the distribution becomes insignificant below 2×10⁶ hrs. Further, the probability of failure in 10 years at 1.5 V, 40°C is much less than 1 in 14,600. This indicates that 100 nm silicon nitride capacitors in this technology have good reliability.