Title :
A Novel Sub-Micron Semiconductor Gap Fill Integrated Processes
Author_Institution :
Leader Univ. Taiwan, Tainan
Abstract :
To investigate the semiconductor process module integration and technology on optimal integrated lithography processes on sub-micron semiconductor process integration. As duel damascene integration copper process is complicated and margin in semiconductor process. It has been common knowledge that pattern collapse of this type process could be prevented by optimal the process module. Proposed novel semiconductor process on various pattern design and deep pattern aspect ratio effects of sub-micron CMOS semiconductor BEOL (Back-End-Of-Line) structure was included in this study.
Keywords :
CMOS integrated circuits; lithography; semiconductor process modelling; BEOL structure; Back-End-Of-Line structure; deep pattern aspect ratio effects; duel damascene integration copper process; integrated lithography process; semiconductor process module integration; sub micron CMOS semiconductor gap fill process; CMOS process; CMOS technology; Fabrication; Integrated circuit interconnections; Integrated circuit modeling; Lithography; Process control; Resists; Silicon; Stress;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-0637-1
Electronic_ISBN :
978-1-4244-0637-1
DOI :
10.1109/EDSSC.2007.4450312
