Implementation of a low-power driver in 65 nanometer CMOS technology

The objective of this paper is to investigate the design and implementation of driver circuits and find out the best fit driver for controlling power transistors. We implemented three drivers in 65 nanometer CMOS technology, and the design criteria for these drivers were mainly focused on reducing the power consumption, which is one of the most important specifications when designing portable consumer electronics. National Instruments Multisim design tool was used to simulate and verify the correct functionality of the designed drivers. While controlling the same power transistors, each of the three drivers ran at 100 MHz clock frequency with an input square wave that had a range between 0 to 1.2 Volts. To obtain the most accurate comparison, we computed the total power consumption of each driver and the same power transistors. The total power consumed by the tapered split-path driver circuit and the tapered driver circuit were 0.30 and 0.22 milliwatts, respectively. The total power consumption of the proposed low-power driver circuit was only 0.12 milliwatts, and the use of this power efficient driver in portable electronics will result in an increased operating time of batteries when compared with the other drivers.