A 2-Level FSK Demodulator for Digital-IF Receiver

Author

Cui, Xiaoxin ; Yu, Dunshan ; Zhang, Xing

Author_Institution

Peking Univ., Beijing

fYear

2007

fDate

20-22 Dec. 2007

Firstpage

1175

Lastpage

1178

Abstract

A 2-level FSK digital demodulator with CORDIC algorithm for digital-IF receiver is presented. The 2-level FSK noncoherent detector is designed based on counting the zero crossing points using new noise elimination technique. Synchronization control information is extracted from the amplitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1 dB with frequency offset 0.1 MHz. The digital-IF receiver including demodulator is implemented based on Xilinx Virtex-II XC2V3000-6FG676 FPGA.

Keywords

demodulators; error statistics; field programmable gate arrays; frequency shift keying; interference suppression; radio receivers; signal processing; synchronisation; BER; CORDIC algorithm; FSK digital demodulator; Xilinx Virtex-II XC2V3000-6FG676 FPGA; digital-IF receiver; noise elimination; noncoherent detector; synchronization control information; zero crossing points; Band pass filters; Baseband; Data mining; Demodulation; Field programmable gate arrays; Frequency shift keying; MATLAB; Mathematical model; Modems; Protection;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Conference_Location

Tainan

Print_ISBN

978-1-4244-0637-1

Electronic_ISBN

978-1-4244-0637-1

Type

conf

DOI

10.1109/EDSSC.2007.4450338

Filename

4450338