High-speed CMOS current-mode equalizers

Proposed in this paper are two key components for a magnetic recording channel detection system: a continuous-time current-mode forward equalizer and a sample-and-hold current-mode backward equalizer. Both are designed for use with the Fixed Delay Tree Search with Decision Feedback (FDTS/DF) detection algorithm. The forward equalizer architecture consists of a bank of bandpass and allpass filters. The backward equalizer uses current steering principles to implement a high-speed robust architecture. Simulations show that an FDTS system utilizing the proposed forward equalizer architecture has performance equivalent to that of a system including an FIR equalizer with 24 taps. A transresistance integrator and transconductance amplifier are used to realize a current-mode, variable-gain integrator building block. This building block is used to implement the tunable bandpass and allpass filters in the equalizer. Simulations based on a 0.8 μm CMOS process show that the forward equalizer is tunable up to 82 MHz. For a given FDTS/DF detection scheme utilizing 2/3(1,7) coding, this translates into approximately 130 to 164 Msamples/s. The corresponding power dissipation is 86 mW from a 3 V power supply. Simulation of the backward equalizer indicates a maximum operating-speed of approximately 100 Msamples/s