Timing recovery for adaptive decision feedback equalization of the magnetic storage channel

Synchronization and timing recovery techniques for adaptive decision feedback equalization of the magnetic storage channel are presented. Only a symbol-rate implementation of the equalizer is considered, since the intent is to operate at speeds as high as possible, given a specific chip technology. In the present case, accurate timing recovery is critical, as the finite-length decision feedback equalizer performance can degrade by 2 to 3 dB with poor sampling-phase choice. A synchronization technique incorporating a (1,3) run-length-limited sequence is presented, and the performances of two steady-state decision-directed timing recovery algorithms are compared. For the overall timing recovery scheme, losses due to typical expected sampling jitter and timing variation on the magnetic disk channel are generally less than 0.5 dB