A Scalable and Reconfigurable Coprocessor for Image Composition

Image composition is an important post processing step in graphics sub system, video sub system and emerging MPEG-4 audio-visual standard. Image composition is achieved by rendering image elements independently with each element has an associated converge information "Alpha". Moving from one application to another i.e. graphics to video or vice versa, hardware architecture for image composition has to change accordingly. Therefore, in this paper, we propose scalable and reconfigurable coprocessor for image composition. We also calculate the operating clock frequency, required system data bus width and number of planes that can be processed in real time for video, graphics and MPEG-4 applications. Verilog implementation and synthesis for 90 nm process shows an estimate of 400 MHz achievable clock frequency and 90 k gates which results in 0.25 mm² silicon area for composition of 3 high definition planes. Simulation model shows that proposed coprocessor can compose 15 high definition planes of size 1920x1080 in real time for 64 bit data transfer on system bus.