Integrating Quartus Wizard-based VHDL floating-point components into a high performance heterogeneous computing environment

One of the newest computational technologies is the high performance heterogeneous computer (HPHC) wherein dissimilar computational devices such as general purpose processors, graphics processors, field programmable gate arrays (FPGAs), etc., are used within a single platform to obtain a computational speedup. Jackson State University has a state-of-art HPHC cluster (an SRC-7), which contains traditional CPUs and reconfigurable processing units. The reconfigurable units are implemented using SRAM-based FPGAs. Currently, the off-the-shelf SRC-7 mechanism for incorporating user components (macros) does not directly support the common case of a multiple file VHDL hierarchy. This research explores a novel approach that allows multiple file VHDL floating-point kernels to be mapped onto the SRC-7. The approach facilitates the development of FPGA-based components via a hybrid technique that uses the SRC Carte compiler in conjunction with multiple file VHDL-based user macros. This research shows how Quartus Wizard-based VHDL floating-point components can be integrated into the Carte development environment.