Low-power, low-jitter direct digital synthesizer with analog interpolation

This paper describes a low-power, low-jitter clock generator for system-on-a-chip (SoC) processors. Low-jitter is achieved by using a ROM-less direct digital synthesizer with analog phase interpolation. Low-power is achieved by using differential and feedback replica bias circuit topologies. A 6-bit resolution prototype is implemented in 0.25 μm CMOS technology. Results demonstrate that the clock generator´s area is 0.12 mm² and it consumes only 1.5 mA of current consumption at 2.5 V. In comparison with other similar state-of-the-art implementations, this represents savings of 37.5× and 5.87× in area and power consumption, respectively.