• DocumentCode
    2986831
  • Title

    Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples

  • Author

    Basu, Shubhankar ; Kommineni, Balaji ; Vemuri, Ranga

  • Author_Institution
    Univ. of Cincinnati, Cincinnati
  • fYear
    2008
  • fDate
    4-8 Jan. 2008
  • Firstpage
    287
  • Lastpage
    293
  • Abstract
    Analog design traditionally relies on designer´s knowldge and expertise. Numerous automated synthesis methods have been proposed over the years; they reduce time complexity and explore wider design space. Manufacturing induced defects in the process parameters, render device characteristics inconsistent with their prediced behavior. Device mismatch causes significant variation in analog circuit performance. Monte Carlo simulation is known to be the most accurate method of measuring performance under random variation. But monte-carlo simulation is prohivitively expensive during synthesis process. In this work we present a novel Spline Center and Range Regression (SCRR) technique on adaptive samples to model performance in the presence of process variation. Mismatch aware macromodels can provide considerable speedup during synthesis with minimal loss in accuracy. Experimental results demonstrate the accuracy of the macromodels on an independent validation set using 180nm and 65nm technologies.
  • Keywords
    analogue integrated circuits; regression analysis; splines (mathematics); Monte Carlo simulation; analog performance macromodeling; device mismatch; process variation; spline center and range regression; Analog circuits; Analog computers; Circuit simulation; Circuit synthesis; Design engineering; Predictive models; Space exploration; Space technology; Spline; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2008. VLSID 2008. 21st International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-3083-4
  • Type

    conf

  • DOI
    10.1109/VLSI.2008.76
  • Filename
    4450516