Title :
An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators
Author :
Ramirez-Angulo, Jaime ; Kalyani-Garimella, Lalitha Mohana ; Garimella, Annajirao ; Garimella, Sri Raga Sudha ; Lopez-Martin, Antonio ; Carvajal, Ramon Gonzalez
Author_Institution :
New Mexico State Univ., Las Cruces
Abstract :
A rail-to-rail differential input stage with programmable threshold levels and offset compensation is introduced. Applications for the implementation of differential and double differential comparators are discussed. Experimental results obtained from a MOSIS 0.5 mum CMOS technology test chip are shown that validate rail-to-rail operation with a 1.5 V supply voltage.
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; comparators (circuits); compensation; MOSIS technology test chip; low-voltage rail-to-rail differential input stage; offset compensated CMOS comparators; programmable threshold level; size 0.5 mum; voltage 1.5 V; Batteries; CMOS technology; Circuit testing; Low voltage; MOS devices; Rail to rail inputs; Rail to rail operation; Switched capacitor circuits; Switching circuits; Very large scale integration;
Conference_Titel :
VLSI Design, 2008. VLSID 2008. 21st International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-7695-3083-4
DOI :
10.1109/VLSI.2008.30
