Generating hardware from OpenMP programs

Author

Leow, Y.Y. ; Ng, C.Y. ; Wong, W.F.

Author_Institution

Dept. of Comput. Sci., Singapore Nat. Univ.

fYear

2006

fDate

Dec. 2006

Firstpage

73

Lastpage

80

Abstract

Various high level hardware description languages have been invented for the purpose of improving the productivity in the generation of customized hardware. Most of these languages are variants, usually parallel versions, of popular software programming languages. In this paper, we describe our effort to generate hardware from OpenMP, a software parallel programming paradigm that is widely used and tested. We are able to generate FPGA hardware from OpenMP C programs via synthesizable VHDL and Handel-C. We believe that the addition of this medium-grain parallel programming paradigm will bring additional value to the repertoire of hardware description languages

Keywords

field programmable gate arrays; hardware description languages; high level languages; parallel programming; Handel-C; OpenMP; field programmable gate arrays; hardware description languages; hardware generation; high level languages; parallel programming; software programming languages; Collaborative software; Computer languages; Computer science; Field programmable gate arrays; Hardware design languages; Multicore processing; Parallel programming; Productivity; Software debugging; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on

Conference_Location

Bangkok

Print_ISBN

0-7803-9729-0

Electronic_ISBN

0-7803-9729-0

Type

conf

DOI

10.1109/FPT.2006.270297

Filename

4042418