Title :
Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route
Author :
Grant, David ; Lemieux, Guy
Author_Institution :
British Columbia Univ., Vancouver, BC
Abstract :
FPGA architects are always searching for more benchmark circuits to stress CAD tools and device architectures. In this paper we present a new heuristic to generate benchmark circuits specifically for incremental place and route tools. The method removes part of a real circuit and replaces it with a modified version of the same circuit to mimic an incremental design change. The generation procedure exactly preserves key circuit characteristics and achieves a post-routing channel width, critical path, and wire length that closely approximates those of the original circuit. Additionally, the method is fast and thus is suitable for use in on-the-fly benchmark generation
Keywords :
benchmark testing; circuit simulation; network synthesis; ancestor control; benchmark circuits; incremental place and route tools; perturber; semisynthetic circuit generation; Benchmark testing; Character generation; Circuit testing; Design automation; Field programmable gate arrays; Stochastic processes; Stress control; Technological innovation; Timing; Wire;
Conference_Titel :
Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
0-7803-9729-0
Electronic_ISBN :
0-7803-9729-0
DOI :
10.1109/FPT.2006.270311